Gaurav Sapkota

Cyber Security Analyst

Electronics Engineer

Systems Engineer

Web Apps Designer

Photographer

Blogger

Gaurav Sapkota

Cyber Security Analyst

Electronics Engineer

Systems Engineer

Web Apps Designer

Photographer

Blogger

Analysis and Verification of MOS Current Mode Logic for logic gate.

Thesis

August 2016 – Dec 2016

Organization: Sharda University, Greater Noida, UP, India.

  • Design a Metal Oxide Semiconductor (MOS) current mode logic which can be used as a logic gate.
  • Simulate the designed circuit using Cadence Tools, PSPICE or LTSPICE.
  • Monitor the performance including heat generated and electricity consumption and prepare detailed report.

Successfully designed the MOS circuit using PSPICE simulator.

Cadence Tools, PSPICE, LTSPICE, Verilog, VHDL, Strategic Planning, Report writing, MS Office.